Differences

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--- papalink [2024/09/19 14:58] – Improve and add text about data lines admin
+++ papalink [2024/09/19 16:01] (current) – [Data lines] Add info about the addresses, speed admin
@@ Line 18: / Line 18: @@
 I2C has two data lines: SDA for data and SCL for the clock signal. The lines are in an open-drain configuration meaning that each connected device can only pull the line down, to 0 V ground, or leave it be at the pull-up voltage. The pull-up voltage in PapaLink is 3.3 V, making PapaLink compatible both with 3.3 V and 5 V logic level circuits.
+Each device must have a 7-bit address that essentially is just an integer number between 0 and 127. PapaLink devices come with a randomized address but with many devices it is possible that these addresses overlap and cause issues. But no worry, it is easy to change the devices address for example by using the PapaLink USB Controller. Purposeful address overlap can be useful as it allows you to control identical devices truly simultaneously.
+The default frequency of SCL is 100 kHz and thus the speed of data transfer is 100,000 bit/s. However the I2C protocol comes up with some overhead. A typical write message to a device consists of a 7-bit address frame to select the right device, 1 read or write bit, and three 8-bit data frames (8-bits for a key and 16-bits for its value). You also have maybe 2 ACK/NACK bits and then bits for the start and stop conditions. So for each 3x8=24-bit of actual data, we have to transfer 36-bits of data so there's ~33% overhead. This 36-bit message we can write at a rate of 2.7 kHz or with a delay of 370 µs. There are some ways we can improve these numbers:
+) More data frames per message (if feasible) will decrease the overhead and increase the overall data transfer rate but will decrease the rate we can switch between devices, thus causing larger delays. 2) When using many data hungry devices it is possible to split the data bus in two or more and use multiple controllers to get more bandwidth (the limit then comes in total USB 2.0 bandwidth available by the host PC when using the PapaLink USB Controller). 3) It is possible to increase the SCL frequency from 100 kHz (standard mode) to 400 kHz (fast mode) and up to 1 MHz (fast mode plus). This increase the transfer speed and reduces delays but may make the bus less stable when running in electrically noisy environments with long or shielded cables, and may require stronger pull-up resistors for the controller. The bus capacitance also should not exceed 400 pF or 550 pF.
+Overall, PapaLink with the 100 kHz frequency fits most of the scientific and industrial speed and latency needs for device control and can be pushed further if really needed. However, it is not enough alone for big data such as high-resolution images and videos or buffered +MHz data acquisition.
 ===== Power lines =====